Pick and Place 文件指南 — SMT 用 Centroid 文件

A pick-and-place (PnP) file — also called centroid file, position file, or .pos/.cpl/.csv depending on the tool — lists every SMT component's reference designator, X/Y center coordinate, rotation angle, and which side of the board it sits on (top or bottom). The SMT assembly machine reads this file to know where to place each part. Format is plain CSV or whitespace-delimited text. Standard columns: Designator, Footprint, Mid X, Mid Y, Rotation, Layer (or Side). Without it, the assembly house has to manually digitize component positions from the Gerber, which costs $50-200 in setup fees and adds a day to lead time.

File > Fabrication Outputs > Component Placement (.pos). Select 'Use auxiliary axis as origin' if you defined one (recommended — sets a known reference point that fab can use for board fixturing). Choose CSV format; ASCII is for legacy machines only. Top and bottom layers export as separate files (project_name-top.pos, project_name-bottom.pos). For JLCPCB SMT, rename to project_name_cpl_top.csv to match their convention. Verify rotations using the 3D viewer before submitting — KiCad rotation conventions differ from many commercial CAD tools.

Altium: File > Assembly Outputs > Generate Pick and Place Files. Choose CSV. Altium's default rotation matches the IPC-7351 convention. Eagle: Run the mountsmd.ulp script (Edit > Run > mountsmd.ulp) — this generates separate top.mnt and bottom.mnt files. Eagle uses ASCII format by default; convert to CSV via spreadsheet for JLCPCB submission. EasyEDA: File > Export > Pick and Place. EasyEDA exports JLCPCB-compatible format directly because it's the same parent company. For all tools, verify rotation conventions before first SMT order.

Two reasons. First, EDA tools and component manufacturers disagree on the 'natural' rotation of each part — KiCad places SOIC-8 with pin 1 top-left, but the JLC library may have it pin 1 top-right. Second, JLCPCB and PCBWay rotate parts in their library at different angles than your EDA tool. The fix: download the part library's footprint preview from JLC's part page, compare to your KiCad/Altium footprint orientation, and add the offset to your CPL file before submitting. JLCPCB's rotation FAQ has a per-package offset table (typical: SOT-23 needs 180°, QFN sometimes 90°).

You don't need a pick-and-place file. Through-hole assembly uses different equipment (wave solder or selective solder) that doesn't read a centroid file. The board outline, drill file, and silkscreen are sufficient for through-hole assembly. If your board mixes SMT (most parts) with a few through-hole parts (connectors, big electrolytics), generate the PnP for SMT only — the assembly house manually places the through-hole parts in a second operation. Mark through-hole parts as 'do not place' in your CPL or simply omit them from the file.