下单前如何确认 PCB 可以生产

No. DRC compares the board against the design rules configured in your own project, which by default are whatever shipped with the software template. They encode nothing about the factory you eventually chose. A 6 mil clearance rule passes DRC forever, whether the fab needs 5 mil or 3.5 mil on the layer count you ordered. DRC is still necessary because it catches shorts and unconnected nets that no manufacturability check looks at, but it answers a question about your intent rather than the factory's capability.

Trace width and spacing below the etch limit come first — traces neck or short and no process tuning saves them. Then drill diameter under the mechanical floor, which pushes you to laser microvias at a different price tier. Annular ring is the one people forget: drill placement has tolerance, so too little copper around a via means the bit breaks out through the pad edge and the connection dies. After that, copper too close to the board outline, since routing and V-scoring have tolerance too. Board size and layer count are cheaper mistakes but still block an order — odd layer counts do not exist because stackups are built from bonded pairs.

0.13 mm is the standard-process floor at both JLCPCB and PCBWay, computed as (pad diameter − drill) / 2. A 0.6 mm pad over a 0.3 mm drill gives 0.15 mm and is comfortably inside spec; a 0.5 mm pad over a 0.3 mm drill gives 0.10 mm and will be flagged. If you are tight on space, enlarging the pad is almost always easier than shrinking the drill, because the drill has its own separate minimum.

Usually not. Lines thinner than the printer resolves and text below roughly 1 mm come out smudged or missing, which makes reference designators useless during hand assembly and rework — but the board is still fabricated and still works electrically. Treat them as a to-do for the next revision. Copper and drill violations are the opposite: hard stops where the fab either rejects the file or silently substitutes a parameter you never asked for.

Open the board file in MakerSuite 3D's viewer and click DFM in the toolbar, then pick your manufacturer. Nine checks run against that fab's published limits and each reports the worst measured value, the number of violating features, and the fix. "Show in 3D" pins every offending feature onto the board so you know where to look back in your EDA tool. KiCad, Gerber, Eagle, EasyEDA, Altium, PADS, P-CAD and Protel 99 files all work, and nothing is uploaded — parsing and calculation happen in the browser tab.

Because the file does not carry the data for it. A Gerber zip exported without the Excellon drill file has no holes to measure, so hole size and annular ring cannot be judged, and reporting them as passing would be worse than saying nothing. The same applies to edge clearance when the outline layer is missing. If something you care about shows as not evaluated, re-export with that layer included — which is exactly what the fab would have asked you for anyway.