PCB 트레이스 폭 계산기 — IPC-2152·IPC-2221

IPC-2221 is the older (1998) standard that gives a single nomograph for current vs. trace width vs. temperature rise, with a conservative 50% derating between external and internal traces. IPC-2152 (2009 update) is based on actual thermal measurements and accounts for: dielectric thermal conductivity, copper plane proximity, board thickness, and via stitching effects. For most modern designs, IPC-2152 produces narrower (more efficient) traces because IPC-2221 was over-conservative. Most online calculators still default to IPC-2221 because the formulas are simpler — but IPC-2152 is the current standard for new designs.

External (top/bottom) traces dissipate heat to ambient air via convection. Internal (mid-layer) traces are surrounded by FR4 dielectric, which has thermal conductivity around 0.3 W/m·K — about 100× lower than copper. Same current, internal traces run hotter, so IPC standards require internal traces to be wider for the same temperature rise. IPC-2221 rule of thumb: internal traces need ~2× the cross-section of external traces for the same current. IPC-2152 refines this by also considering nearby copper planes (which act as heat sinks).

Common targets: 10°C rise for high-reliability or thermally tight designs, 20°C rise for general consumer electronics, 30°C rise for cost-driven designs with margin. Higher rise = narrower trace = less copper but more heat. Critical: temperature rise is on top of ambient and the rest of the board's thermal load. A board running at 60°C ambient with 30°C trace rise puts the trace at 90°C — close to FR4's Tg (typically 130–170°C). For automotive or industrial (high ambient), use 10°C rise. For desktop electronics, 20°C is standard.

Copper weight is specified in oz/ft² and translates to thickness: 0.5oz ≈ 17.5μm, 1oz ≈ 35μm, 2oz ≈ 70μm, 3oz ≈ 105μm. Doubling copper weight roughly halves the required trace width for a given current (the cross-sectional area drives ampacity). Standard JLCPCB external is 1oz, internal is 0.5oz. For higher-current designs (>3A), upgrade to 2oz outer (~$5 surcharge) before widening traces, because wider traces eat routing density faster than copper weight upgrades cost.

These are independent constraints. Impedance-controlled traces (50Ω single-ended, 90Ω/100Ω differential) are sized by: dielectric thickness, Dk, and reference plane distance — not by current. Power traces are sized by ampacity: current, copper weight, temperature rise. They never compete because high-speed signal traces carry milliamps (no thermal issue) and power traces carry amps (no impedance issue at DC). The only overlap is when a single trace carries both, which is rare. Calculate impedance first if signal integrity matters, then verify ampacity is satisfied at the calculated width.