Differential Pair Routing Guide — Length Matching and Impedance

High-Speed Routing Without the Trial and Error

USB 3, PCIe, HDMI, Ethernet, MIPI, DDR — every modern interface uses differential pairs because differential signaling rejects common-mode noise and supports the data rates that single-ended signaling cannot. But differential routing has rules that single-ended doesn't: matched lengths, controlled differential impedance, and tight intra-pair skew limits. This guide covers the rules per interface and how to verify your routing matches the specification before fab.

What Makes a Differential Pair

A differential pair is two traces routed close together with equal-and-opposite signals. The receiver subtracts (Pos − Neg) to recover the signal, which cancels any noise that hit both traces equally. The pair has two impedances that matter: Zdiff (differential impedance, ~85–100Ω depending on interface) and Zcm (common-mode impedance, less critical). Zdiff is set by trace width, trace spacing, dielectric Dk, and reference plane distance. The fab's stackup spec defines the geometry that hits your target Zdiff at your chosen S/W ratio.

What This Guide Covers

• Per-interface Zdiff — 85Ω PCIe, 90Ω USB 2/3, 100Ω HDMI/DisplayPort/Ethernet/MIPI/LVDS/SATA.
• Intra-pair skew — limits per interface (5 mil USB 3, 2 mil PCIe Gen4) and how to meander-match.
• Inter-pair skew — looser tolerance, why receivers correct it (PCIe LTSSM, DDR write leveling).
• Layer transitions — how to match via count between + and − traces; ground stitching vias.
• Tight vs loose coupling — S ≤ W vs S > 2W tradeoffs for noise immunity vs flexibility.
• Length-matched routing — KiCad/Altium/EasyEDA tuning meanders, where to place them.

How to Verify Differential Pair Routing

1. Open pcbviewer.app and drop your PCB file. The parser extracts net names — differential pairs are usually suffixed _P/_N or +/-.
2. Use the Net search to find pair members. Highlight both traces; the viewer shows them in matched colors.
3. Use the measurement tool to compare lengths between + and − traces. Skew under your interface limit (e.g. 5 mil USB 3)?
4. Verify both traces of each pair share the same layer for most of their length. Layer transitions should match via count between + and −.
5. For Zdiff verification, check trace width and spacing against your fab stackup spec. Geometry mismatch = impedance miss = signal integrity risk.

Why Differential Routing Discipline Matters

Differential routing failures are subtle. A 10 mil intra-pair skew on a USB 3.0 link won't fail enumeration — it will fail at maximum cable length, on certain hosts, intermittently, in ways that look like host or cable problems. By the time you've narrowed it to your board, you've shipped product. A correctly routed pair is permanent insurance against these subtle failures. The work is in the discipline, not the analysis — once you have the rules, every project applies them automatically.

When Differential Routing Bites

• USB 3 hubs and front-panel cables — any extension that adds skew to an already-tight budget
• PCIe risers and edge connectors — every connector adds layer transitions that must match
• DDR4/DDR5 — strobe pairs need 2 mil intra-pair, byte lanes need length matching within byte
• Ethernet 1000BASE-T — four pairs at 100Ω each, with strict pair-to-pair length matching for PHY equalization
• MIPI CSI/DSI — clock and data lanes need both length matching and signal-to-clock skew control

Browser-Side Parsing, No Upload

High-speed routing details disclose sensitive engineering — interface choices, performance targets, and stackup decisions are all competitive intel. MakerSuite 3D parses your PCB file entirely in your browser. Net names, trace lengths, layer assignments, and via locations stay on your machine. Safe for NDA reviews, defense applications, and pre-release product reviews.